The Flip-Chip technology is an advanced package technology for connecting chip and substrate. During packaging process, the chip is “flipped” and so the pads of the chip connect with the pads of the substrate. The materials of substrate suitable for Flip-Chip generally include ceramic substrate, silicon wafer, polymer, glass and so on. The flip-Chip technology thereof is widely applied in RF components, sensors, microprocessor, CCD, semiconductor lasers, LED, SAW (surface acoustic wave) device, Multi-chip Modules (MCM), etc., which is used for computer, PCMCIA card, martial equipment, personal communications, clocks, watches, LCD, and so on.
Flip-Chip technology has two main advantages. First, the signal transmitting distance between a chip and a substrate can be reduced and so it is suitable for packaging a high-speed device; second, the size of the packaged chip can be reduced as the size of chip before packaging, so it is suitable for the IC device requiring a smaller packaging size.
In those conventional arts, the Flip-Chip package structure of electronic devices is accomplished by forming bumps on pads of the surface of electronic devices (or on the substrate side), and connecting those bumps to pads on the substrate side (or the surface of electronic devices). After the Flip-Chip packaging, the gap between each electronic device and the substrate is sealed with resin to ease stress, to prevent the invasion of foreign matter, and to protect the bumps. However, if any foreign matter sticks to the surface of a GaAs element or a surface acoustic wave element, which is operable at a high frequency, the desired electric characteristics cannot be obtained, and therefore the gap between the substrate and the element should have an airtight structure, with the element covered by a resin all around.
To meet this requirement, a structure, in which the gaps between the substrate and the electronic devices are made airtight, is formed by dropping a resin of high viscosity type, which would not enter into the gaps between the substrate and the electronic devices, on the electronic devices and hardening it.
However, in a structure wherein Flip-Chip package electronic devices are covered with resin, signals often cannot be transmitted and fail to achieve the desired characteristics, since the resin enters through the gaps between the substrate and the electronic devices to come into contact with an active region of the electronic devices.
To avoid the aforementioned problem, in the U.S. Pat. No. 5,969,461, it discloses a structure of Underfill package technology. Referring to FIG. 1A, the resin 140 will flow into the space between the acoustic wave device 110 and the substrate 120 during the time from injecting the resin 140 to the resin 140 having been cured. Therefore, the dam 130 is disposed on the substrate 120 within the periphery 122 of the acoustic wave device 110 and interconnections formed by stud bumps 123 and conductive materials 124 for avoiding the resin 140 contacting with the active region of the acoustic wave device 110 and affecting the characteristic of the acoustic wave device. However, because the dam 130 is disposed within the stud bumps 123 and the conductive materials 124, the specific position relationships among the dam 130, the stud bumps 123, and the conductive materials 124 must be accurate, which increase a complexity of the process. Furthermore, the dam 130 is close to an active region of the acoustic wave device 110 and when the dam 130 does not abut a face 114 of the acoustic wave device 110, the resin 140 easily contacts with the active region as long as the resin 140 lightly flows over the dam 130.
Referring to FIG. 1B, the U.S. Pat. No. 6,262,513 discloses another encapsulation resin package technology. A resin layer 240 covers on an electronic device 210 and the substrate 220. A fluiding of the resin layer 240 must be low or no flow for avoiding flowing the resin layer 240 into the space between the electronic device 210 and the substrate 220 and affecting the characteristic of the electronic device as the Underfill package technology. Nevertheless, the resin layer 240 has the problem of thermal expansion when heating to cure the resin. A SiO2 is added into the resin layer 240 in order to reduce a thermal stress due to the difference of thermal expansion coefficient, but it results in decreasing the adhesion between the resin layer 240 and wires 290 and the hermeticity of the structure is so unsatisfactory.
In the U.S. Pat. No. 6,448,635, is also discloses a structure of Underfill package technology. As shown in FIG. 1C, a distance D1 between active region 340 and the adjacent peripheral surface 338A or 338C is more than 550 μm, and a distance D2 between each peripheral side surface 338B or 338D and the active region 340 is more than 200 μm. Referring to FIG. 1D, these distances prepare against the flowing of an encapsulant 306. Therefore, the encapsulant 306 extends under SAW device 332A, but the encapsulant 306 does not extend inward from each of surfaces 338A and 338C more than 550 μm. Therefore, the area of not active region is very large and, the packaged size will increase.